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Traffic Light Controller in Verilog

A finite-state traffic controller implemented in RTL

  • Verilog
  • RTL
  • FPGA

Overview

This project uses a finite-state machine to coordinate a traffic-light sequence in synthesizable Verilog. The design emphasizes clear state transitions, timing behavior, and verification.

Project details

Additional RTL diagrams, simulation waveforms, and implementation notes are coming soon.